1. Field of the Invention
The present invention relates to an electronic component package including a plurality of chips and a plurality of external connecting terminals and a method of manufacturing the same, and to an electronic component package substructure that is used for manufacturing the electronic component package.
2. Description of the Related Art
A reduction in weight and an improvement in performance have been desired for mobile apparatuses represented by cellular phones and notebook personal computers. Higher integration of electronic components used for mobile apparatuses has been sought, accordingly.
A system large-scale integrated circuit (LSI) and a multi-chip module have been known as highly integrated electronic components. The system LSI is a single integrated circuit (IC) in which functions of various electronic components are incorporated. The multi-chip module is a module made up of a plurality of chips integrated through the use of a wiring substrate, for example.
The system LSI has a benefit that it allows the integration density to be higher and the number of leads to be minimized. On the other hand, the multi-chip module has a benefit that it facilitates the implementation of a single module having desired functions by integrating a plurality of chips having different functions.
A description will now be given of a conventional method of manufacturing an electronic component package including at least one chip and a plurality of external connecting terminals, such as a system LSI or a multi-chip module. In a typical conventional method of manufacturing an electronic component package, at least one chip is mounted on a base such as a wiring substrate prepared for a single electronic component package, a terminal of the chip is connected to an external connecting terminal, and the connecting portion between the terminal of the chip and the external connecting terminal is sealed. The connection between the terminal of the chip and the external connecting terminal is performed by wire bonding or flip-chip, for example. In a case where flip-chip is employed, the terminal of the chip and the external connecting terminal are connected to each other through a lead inside the wiring substrate. Wiring among chips in the multi-chip module is also performed by wire bonding or flip-chip, for example.
JP 2001-035993A discloses a multi-chip module in which a bonding pad connected to a chip is connected to a lead that is an external connecting terminal by wire bonding. JP 2001-035993A further discloses a technique of forming inter-chip wiring and the bonding pad through a wire-forming process. According to this publication, the wire-forming process includes a film forming step, a lithography step and an etching step, for example.
JP 2001-244403A discloses a technique wherein inter-chip wiring and pads for external connection of a multi-chip module are formed through a wafer process. According to this publication, the wafer process includes a series of steps of forming an insulating layer, forming via holes, embedding plug metals, flattening, forming films by sputtering, and forming a wiring pattern through photolithography techniques.
U.S. Pat. No. 5,926,380 discloses a method of manufacturing a chip-size semiconductor package as will now be described. In this method, first, a lead frame is bonded to the top surface of a wafer in which a plurality of semiconductor chips each having a plurality of pads on the surface thereof and aligned with chip partition lines are formed. Next, leads of the lead frame and the pads of the semiconductor chips are connected to each other by wire bonding. Next, the top surfaces of the leads closer to the base ends are exposed and the top and bottom surfaces of the wafer are molded. Next, conductive metallic plating is performed on the exposed top surfaces of the leads closer to the base ends. Next, the wafer and the lead frame are cut to complete the semiconductor packages.
In the typical conventional method of manufacturing an electronic component package, a series of steps, such as mounting of at least one chip on the base, connection of the terminals of the chip to external connecting terminals, and sealing of the connecting portions between the terminals of the chip and the external connecting terminals, are performed for each electronic component package. This typical method has a problem that it is difficult to mass-produce electronic component packages at low cost in a short period of time.
The method of manufacturing a chip-size semiconductor package disclosed in U.S. Pat. No. 5,926,380 makes it possible to mass-produce chip-size semiconductor packages at low cost. In this method, however, to alter the specifications of semiconductor chips, it is required to start with design of a wafer including a plurality of semiconductor chips. Therefore, the method has a problem that it is difficult to respond to alterations to the specifications flexibly and quickly. In addition, it is impossible to manufacture multi-chip modules through this method.
JP 2003-163324A discloses a method of manufacturing a three-dimensional layered semiconductor device as will now be described. In this method, first, a plurality of three-dimensional layered semiconductor devices are formed on a provisional substrate. Next, the provisional substrate is removed from the aggregate of the three-dimensional layered semiconductor devices. Next, the aggregate of the three-dimensional layered semiconductor devices is diced to separate the plurality of three-dimensional layered semiconductor devices from one another. In this method, external electrodes are formed on at least one of the top surface and the bottom surface of each of the three-dimensional layered semiconductor devices.
The method of manufacturing a three-dimensional layered semiconductor device disclosed in JP 2003-163324A enables mass production of three-dimensional layered semiconductor devices capable of achieving higher integration. According to this method, however, it is necessary to perform the steps of removing the provisional substrate and forming the external electrodes, and therefore this method has a problem that a large number of steps are required.